“DOWN with the deadly rhythm of the production line,” proclaimed the revolutionary posters in Paris in 1968. In reality, those French demonstrators had less to complain about than they thought, because when you look closely industrial production lines often do not have much rhythm at all.
In fact, the whole notion that automated assembly lines are relentlessly efficient is a fallacy. It can be mind-bogglingly hard to coordinate the flows of products through several processing steps, or to deliver a multiplicity of components exactly when and where they are needed. A small glitch in one part of the system can wreak havoc downstream, with the result that finished products often emerge at a distressingly erratic rate.
Such inefficiencies cause manufacturing companies enormous headaches – and enormous losses. The microprocessor giant Intel estimates that it could save around $1 billion a year if only it could optimise the flow of its silicon chips through the production process. Despite intensive studies of the problem, no one has been able to come up with a solution – until now, perhaps.
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If manufacturing industry has found its salvation, it has come from an unexpected quarter. Dirk Helbing, a physicist at the Dresden University of Technology, had previously helped pioneer the understanding of traffic flows, and the insights and models that he and other physicists have provided are changing the way German roads are managed. Now, at the request of a German chip manufacturer, Helbing has turned to the flow of items on the production line. The result could be order in place of turmoil, increased efficiency, and a welcome hike in profits.
To produce circuit patterns on the silicon wafers that are eventually cut up into individual chips, the wafers have to be dipped into a succession of chemical baths. Between each dip the wafer is washed, and at the end of it all it is dried. The whole process is automated, with wafers transported from one bath to the next by a gripping mechanism called a handler. Each handler serves several batches at once, and the challenge is to coordinate its movements to generate a high throughput of wafers while still doing everything at the right time. There is some leeway in the time each wafer can be left in a particular bath, but if the handler pulls it out too quickly, or leaves it in too long, the wafer is ruined.
Synchronised chips
Munich-based silicon chip manufacturer Infineon Technologies wanted to find the best way to synchronise the handler’s movements. Traditionally, the problem had been dealt with by building substantial waiting times into the schedule. But this meant that each batch of wafers spent about as much time waiting to be transferred to the next stage of the process as it did actually undergoing chemical treatment – an obvious waste of time and money.
Helbing came onto the scene thanks to Dominique Fasold, a student working for her master’s degree in the logistics of production flows. Financed by Infineon, Fasold approached the university at Dresden to find a supervisor. When Helbing heard about her project he realised his traffic work might help.
His traffic simulations set up a collection of rules to model the movement of cars and lorries along a virtual road. The model successfully reproduces traffic flows seen in the real world – including jams and bottlenecks (żěè¶ĚĘÓƵ, 15 January 2000, p 34). But while you can’t force drivers to act in a way that will unblock a congested motorway, you can control the way silicon wafers move down the production line. In theory, Helbing reasoned, Infineon’s problem should be solvable.
So he and Fasold decided to collaborate. They began their analysis by looking at the simplest production process: a linear sequence where each stage receives items, and then dispatches them to the next stage. How should each step respond to any changes in the input rate?
In traffic all the responses are “local” – a driver can only see and adapt to what the vehicles nearby are doing – in a production line it is possible to monitor what is happening further away in the process and to take that long-range information into account. By fine-tuning how the various steps of the chain respond to fluctuations in input, Helbing’s simulations showed he could reduce or even eliminate the irregularities in flow.
The simulations showed that the best coping strategies were those that took account of what was happening further down the line, such as slowing down a particular step in response to congestion ahead. Responses that were heavily dependent on what was happening upstream, in contrast – such as slowing down one stage when you know it is not going to receive its next input on cue – tended to make the system less stable and increased irregularities in the flow, instead of smoothing them out.
Of course, most real-world production processes are more complex than a simple linear chain of steps. For example, an item in the flow might at one point be routed towards several different end products, such as when a basic chip is modified in different ways to produce different circuits. In other words, the flow scheme branches. So Helbing and Fasold looked at how their model worked for other patterns of connection, or topologies, between the various steps in the process.
Different topologies, it turns out, can generate very different behaviours. For example, ladder-like networks, in which products are shunted down two parallel chains as well as from one chain to the other, are far less prone to congestion than linear chains or hierarchical, tree-like networks, because they contain alternative ways of getting to the same point in the scheme; bottlenecks can be avoided by shrewd rerouting.
Infineon’s handlers have to deal with several production batches at once, so optimising their performance involves stringing various tasks together: in effect, this too is a problem of topology. By optimising the parameters in their model, such as dip time and speed of movement between tanks, Helbing and Fasold were able to come up with a sequence that reduced or even removed the waiting time between transfers (see Diagram). When this sequence was implemented at the Infineon plant, the throughput of wafers typically leapt by around 33 per cent.
Curiously, in the redesigned schedule the actual treatment times – how long wafers spent in each bath – were slightly longer than they were before. In other words, the solution was not to try to rush the wafers through the baths as quickly as possible, but to give them a series of more leisurely dips, as this cut the time spent queuing in-between.
It is not just Infineon that is benefiting from these insights. The packaging division of the Swedish paper products company SCA, for instance, is using the same approach to tackle the company’s flow-scheduling problems with their paper corrugators. Dick Sanders of SCA’s Brussels division read about Helbing’s traffic work and saw its relevance to the company’s problems. Now the company has recruited Helbing’s help, and is using his ideas to improve the way their processes are organised.
And what about the billion dollars that Intel could potentially save? “We’d be willing to contribute to solving these inefficiencies,’ Helbing says. “With funding for PhD projects, we could certainly achieve much more.”
Does anyone have Intel’s phone number?
