IF YOU have ever grumbled that your life seems to be ruled by the ticking of the clock, spare a thought for those who design silicon chips for a living. Almost every feature of a processor chip 鈥� the speed at which it shifts data, the layout of its connections, even the amount of power it consumes 鈥� is dictated by a silicon clock that beats time like a hyperactive conductor.
But what if chip designers could ditch the clock? This seemingly unlikely option is being investigated by manufacturers as a way of solving the problems that come with larger and faster chips. The chips of the future could be far better off without the master clocks that govern their workings. This new generation, known as asynchronous chips, will have circuits that can run as fast or as slow as they like. You might even have one in your pocket right now 鈥� asynchronous circuits are already appearing in pagers and smart cards, and they could eventually end up inside everything from superfast computers to mobile phones.
These days the clock inside a top-of-the-range processor chip gallops along at about 2.8 billion beats a second (2.8 gigahertz) and everything the chip does is in step with this signal. There are all kinds of advantages to this approach. Because all parts of the chip operate to the same rhythm, they work easily together and the output of any one part can form the input to another. This makes them relatively straightforward to design.
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But these synchronous chips have some serious disadvantages too. They move data about in much the same way as a line of people passing buckets along in time to the beat of a drum. On the first beat, each person in the chain grabs a bucket from the person behind them. On the second beat they pass the bucket forward to the person in front, and so on. However, the chain keeps on working regardless of how much water is in each bucket. Some may be empty. And since all buckets move at the same rate, the 鈥渃lock speed鈥� of the entire system 鈥� the rhythm of the drum 鈥� cannot be faster than the rate at which the slowest person in the chain can work. This can make synchronous chips inefficient. A real chip has many 鈥渂ucket brigades鈥� acting in parallel, and if several finish their tasks early they have to wait for the next beat of the drum before they can continue.
Making and distributing the clock signal around the chip is also a costly business, eating up to 30 per cent of the chip鈥檚 power supply. The clock must always be on, even if the chip is idle, and this generates heat that has to be dissipated somehow. This makes synchronous chips power-hungry and can significantly reduce the battery life of mobile devices. And since the movement of electrons inside a conductor generates radio waves, the clock signals can broadcast significant amounts of electromagnetic noise at the frequencies at which the chips operate, and their harmonics. This noise can interfere with other electronic devices such as navigation equipment on aircraft, life-support machines in hospitals and even other parts of the same device. Increasingly, the makers of mobile devices are having to shield them to prevent interference.
Most challenging of all, however, is the size of modern chips. As they get larger and clock speeds get faster, distributing a time signal around them gets more difficult. The distances the signal has to travel are becoming so large 鈥� the time it spends in transit can be several times longer than that needed by a transistor to carry out a single logic operation 鈥� that parts of the chip close to the clock end up out of step with parts that are further away. Clearly, when different parts of the orchestra are out of step, the result is chaos.
One of the best solutions is to get rid of the global time signal altogether and let different parts of a chip run at their own speed. By doing away with the clock, asynchronous chips allow packets of data to be passed as fast as each part of the chip can process or move them. A final calculation can take place as soon as the precursor calculations have finished, for example, since circuits aren鈥檛 left hanging around waiting for the next tick of the clock.
For this to work well the movement of data packets must be coordinated, and this is made possible with special circuits. The most important type was developed in the 1950s by David Muller, then a computer scientist at the University of Illinois. Called the Muller C-element, it鈥檚 a small circuit that acts like a signal box on a railway. It responds to the arrival of data packets, allowing them through or halting them briefly to prevent collisions and minimise delays (see Diagram). This means that a chain of Muller C-elements can impose order on circuits that have no timing signals. And because there is no need to wait for a timing signal, the speed of a chip using these devices depends entirely on how fast the data can move.
Jim Garside, a computer engineer at the University of Manchester 鈥� a leading centre in asynchronous chip design 鈥� says this makes chips 鈥渃orrect by design鈥�. Put the data in and the calculation will proceed at whatever rate the chip can manage. 鈥淏ut if the timing isn鈥檛 right in a synchronous chip, the whole thing falls over.鈥�
But don鈥檛 expect gadgets built entirely from asynchronous chips any time soon: the computer industry has a huge amount invested in synchronous design, and will not be rushing to replace every part of a chip with an asynchronous alternative. So designers are developing devices that take the best of both worlds. These are known as GALS or globally asynchronous locally synchronous chips. In GALS chips, the asynchronous mechanism is responsible for moving data from one part of the chip to another 鈥� from the signal processor to the working memory, for example. But each part of the chip generates its own timing signal and operates at its own speed.
This makes life much easier for chip designers. In a conventional chip, every part must be designed to work at the same speed, or at fixed fractions of it, to remain in exact synchrony. So if one circuit is upgraded to allow it to run faster, the whole chip usually has to be redesigned. But with GALS, engineers can combine older designs with new and faster ones. Given the difficulty of building entirely new memories or signal processors, this could lead to massive savings in the development of new chips, and promises to help designers making the next generation of superfast computers (see 鈥淣iobium speedsters鈥�).
GALS designs have a string of other advantages too. Since the data bits aren鈥檛 sent down connections at a regular rate, thieves find it more difficult to beat the security on smart cards built using this technology (see 鈥淪mart savers鈥�). Nor do GALS devices produce intense electromagnetic noise at one specific frequency and its harmonics like conventional chips, since different parts of the GALS chip work at different speeds. Instead, the total noise is spread across the frequency spectrum, making interference less of a problem. Finally, whenever the chips are idle they use less power, and they also generate less heat and so do not require complex mechanical cooling fans, making them more attractive to the makers of mobile devices.
Devices that use asynchronous components are already hitting the marketplace. The Dutch electronics giant Philips has developed an asynchronous microchip for smart cards and for pagers, for example. The problem with pagers that use conventional chips is that they have a receiver to listen out for radio signals, but these can鈥檛 always operate at the same time as the pager鈥檚 microchip because of the electromagnetic noise it generates. But with the reduction in noise that an asynchronous design allows, Philips has produced a pager that searches for signals continuously, and which uses less power, so its batteries last longer.
Niobium speedsters
Super-cold chips that keep their own time
At the University of California, Berkeley, Ted Van Duzer鈥檚 supercharged chips sit in a bath of bubbling liquid helium. In principle, says Van Duzer, his designs could operate at up to 50 gigahertz. And an asynchronous design might be just what is needed to make them work.
His plan is to build a special circuit using the metal niobium. Cooling it almost to absolute zero in liquid helium turns niobium into a superconductor. For binary data, his circuit will generate extremely narrow pulses 鈥� lasting a picosecond or so 鈥� that the chip will be able to process at a rate of tens of billions a second. And since superconducting circuits are free of resistance, the pulses will take very little power to create. 鈥淚t鈥檚 the most promising technology beyond silicon for low-power, high-end computing,鈥� he says.
At such extreme speeds, however, transmitting an accurate timing signal to coordinate activity around the niobium chip becomes a nightmare. Tiny variations in the size of the component circuits lead to big variations in the accuracy of the timing signals as they race through the chip. Instead, he says, the best solution is to ditch the master clock and use a GALS design instead.
This way, the data will move from one part of the chip to another at whatever speed it can manage, because the circuits in each subsection of the chip have their own clock. His group has already designed chip components that operate at 38 gigahertz, and Van Duzer says speeds of up to 50 gigahertz should be possible.
Just how popular this type of computer could become is hard to say. It may be difficult to persuade computer manufacturers to change from silicon at room temperature to helium-cooled niobium. But with such a huge potential gain in speed, some chip makers may find Van Duzer鈥檚 design irresistible.
Smart savers
Drop the clock to keep your money safe
The prize for a thief who discovers how to extract data from smart cards is so great, a flaw was bound to be discovered sooner or later. Fortunately, researchers from the University of Cambridge beat the thieves to it this year when they found a way to crack the cards using little more than a flashgun and a microscope. The Cambridge group鈥檚 solution is to redesign the cards using asynchronous technology.
Smart cards look much like ordinary credit cards except for a small printed circuit visible on their surface. This circuit acts as the input and output for a microchip embedded in the card beneath. The chip usually contains a microprocessor and a few kilobytes of memory to store information such as the cryptographic key for encoding the flow of data in and out of the chip, and individual details such as PIN numbers.
Although the cards have a number of security devices to protect this data, a stolen card is particularly vulnerable to a type of attack known as differential power analysis, in which the power used by the chip is correlated with the data passing in and out of it. For example, the 1 of binary code is represented by the presence of a high-voltage pulse whereas the 0 is represented by a low-voltage pulse or the absence of a pulse. If the clock speed of the device is known, it is relatively straightforward to work out the sequence of 0s and 1s being processed simply by looking at changes in the power output of the chip.
To help prevent this kind of attack, Simon Moore and his colleagues at Cambridge propose using two wires instead of one to get data in and out of the chip, a system known as dual rail encoding (see Diagram). To transmit data, for example, the chip sends the signal down both wires: a 0 down one wire and a 1 down the other indicates a 1, and the converse indicates 0. This allows the chip to recognise binary bits without reference to a time signal. Whether 0 (10) or 1 (01) is transmitted, the total power output from the chip is the same. This shields the data stream from attack by differential power analysis.FIG-mg23655802.jpg
It also protects against other forms of attack. One method is to measure the output of the smart card and then electronically invert the contents of one of the chip鈥檚 memory cells and measure the output again to see how this has changed the signal. Repeat this process and you can eventually work out the smart card鈥檚 key. What Moore鈥檚 group found was that it is possible to etch away a layer of the chip to expose the memory cells and then flip them with a flash of light focused down a microscope.
While dual rail technology can鈥檛 prevent this, it does provide a way to warn that such an attack is in progress. If the memory cells are flipped at random, then some of the bits sent along the dual rails will also be flipped. So instead of sending 01 or 10, the chip will sometimes send 11. Chips can be programmed to spot this as a warning of attack.
In addition, an asynchronous design allows programmers to insert random delays into the chip output to further confuse hackers. 鈥淲e鈥檝e presented our design to a number of smart card manufacturers and it has been well received,鈥� says Moore. How long it can withstand the attacks of sophisticated electronic thieves remains to be seen.
Faster and faster
Who wins out when the clocks are gone?
Earlier this year, an unseemly fracas broke out between two of Silicon Valley鈥檚 biggest corporate residents 鈥� Advanced Micro Devices and Intel, the world鈥檚 two largest makers of processor chips. Their dispute was over a traditional measure of silicon machismo: whose chips are the fastest. The melee gave an insight into Silicon Valley鈥檚 chip culture, but it also hints at the arguments that might begin with the advent of asynchronous chips and why some manufacturers may ignore asynchronous chips regardless of their advantages. After all, how can you judge the speed of a chip with no master clock?
It all started when AMD claimed that its flagship Athlon XP 2000+ chips were quicker than the Pentium 4 2A chips made by its rival. To back up its claim AMD pointed to the results of a battery of tests known as SYSmark 2001 that was an industry benchmark for measuring the performance of chips. By this measure the Athlon XP 2000+ outperformed the Pentium 4 2A, even though AMD鈥檚 chip clock operates at 1.67 gigahertz and Intel鈥檚 at 2 gigahertz. This result is an important part of AMD鈥檚 campaign to challenge what it calls the 鈥渕egahertz myth鈥�, that chips with faster clock speeds are necessarily better. But Graham Parker of Intel UK says his company鈥檚 chips are faster on other major industry benchmarks.
Then in January, a new benchmark was introduced called SYSmark 2002 in which the tasks to be performed had been changed. The red mist descended when it emerged that in the ratings war, AMD鈥檚 Athlon chips had suddenly fallen behind their rivals, although all that had changed was the benchmark.
AMD then discovered that some tasks at which the Athlon XP chips excelled had been removed from SYSmark 2002 and others added 鈥� tasks at which the Pentium 4 chips were known to be better. Intel is a member of the consortium of companies that develops the SYSmark benchmark, but at the time AMD was not. To some, including AMD, this looked as if the supposedly independent benchmark had been changed to boost the Pentium 4 ratings. Palmer denies this: 鈥淲e can鈥檛 manipulate the benchmark. SYSmark is put together by a group of companies, not just Intel. The argument rumbles on to this day.