FRUSTRATED? Irritated? Spending too much time waiting for your PC to catch
up with your typing? The solution, as the sales assistants at your local
computer store will tell you, is a new, faster machine. They know they are on
safe ground with this advice because ever since PCs came into being they have
grown steadily faster. But now the computer industry is starting to worry that
this trend may be coming to an end. Could it be that sales staff may soon have
to change their patter?
Electronics manufacturers have ensured that each generation of computers is
faster than the last by squeezing more transistors and other components onto
their microprocessor chips. That has meant making each component smaller and
smaller. More transistors means more speed: today鈥檚 processors can update
graphics and search databases faster than ever. Today, transistors are
typically 0.6 micrometres in across, and companies such as Digital and
AT&T have started making chips with components a mere 0.35 micrometres
across. But miniaturisation cannot continue forever. Even when pushed to the
limit, today鈥檚 manufacturing techniques will not be able to produce
transistors smaller than about 0.1 micrometres. Researchers reckon the end of
the road could come about 15 years from now.
The 0.1 micrometre limit is dictated by a number of economic and technical
constraints. To set up a competitive fabrication plant to make leading-edge
chips already costs about $1 billion, says Steve Furber, professor of
computer science at the University of Manchester. 鈥淵ou have to sell an awful
lot of chips to pay the interest on that.鈥� This entry price is expected to
grow as the elements of a chip get smaller, and fewer companies are likely to
put up the money. On the technical side, the ultraviolet light used to etch
components onto raw silicon wafers cannot produce sharp images below 0.1
micrometres. To create smaller components would mean switching to X-ray or
electron beam techniques, which are proving costly to develop.
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With the limits of miniaturisation in sight, researchers are looking at
other ways of squeezing more processing power out of a chip without having to
build in smaller components. In the late 1980s, the way ahead seemed clear.
Innovations such as reduced instruction set computer (RISC) chips, created big
jumps in processing power and have been widely adopted. But what comes next is
far from clear.
The range of operations that a chip can carry out without help from outside
is dictated by its instruction set. It can take a piece of data from one
memory register, for example, add it to another piece of data, and store the
result in another register. Each operation is carried out according to an
instruction. In some ways a microprocessor is like a restaurant, and its
instruction set is a recipe book. In the 1980s, computer makers realised that
the recipe book had grown too large. Many simple instructions had been strung
together to create compound instructions, such as 鈥渏ug a hare鈥�, that are
rarely if ever used. The penalty of this approach is that a chef has to waste
time flicking through the massive recipe book to discover how to carry out
even the simplest of tasks. Also, it turns out that it is often quicker to
have separate chefs carrying out single operations than one chef doing a
string of them.
So a number of computer manufacturers, notably IBM, came up with RISC,
which took a hatchet to the cookery book. They designed chips to work with a
slimmed-down instruction set, and transferred the task of building up compound
instructions to the compiler 鈥� the software that translates the user鈥檚
programming needs into instructions that the microprocessor can deal with.
Removing complex operations from the instruction set led to a five-fold
increase in performance.
With the advent of RISC processors, the old-style chips came to be known as
complex instruction set computer (CISC) devices. The Intel chips used in
standard PCs fall into this category. But really the only thing complex about
them is the larger instruction set, and even that difference is now
disappearing as RISC instruction sets have started to grow. 鈥淭here is very
little that is useful now left out of RISC,鈥� says Dominic Sweetman, director
of the London-based chip consultancy Algorithmics.
One of the main benefits of RISC is that it opened the door to a new way of
carrying out instructions. With the exception of a few devices (see 鈥淭hrow
away the clock鈥�), all chips regulate the rate at which they perform tasks with
an internal timer. CISC chips take on a maximum of one instruction every tick
of their built-in clock, and often they cannot even keep up this rate because
they must complete one instruction before taking another.
Omelette, salad and chips
With RISC, things work differently. Every time the clock ticks, the chip
takes on a new instruction and performs the first part of it. When the clock
ticks again, it takes another new instruction and carries out the next part of
the first instruction. It is as if the kitchen is regulated by a person who
calls 鈥渃hange鈥� at regular intervals. If the order is for an omelette, salad
and potatoes, then on the first call the eggs are cracked into a bowl, on the
second the potatoes would be washed and eggs beaten, on the third the lettuce
would be washed, the potatoes peeled and the seasoning added to the eggs, and
so on.
Using this technique, called pipelining, the processor can complete as
many as eight instructions every time the clock ticks.
The way in which RISC splits each recipe into more manageable tasks is a
big advantage, Sweetman says. It has allowed manufacturers to build bigger,
more powerful processors simply by adding another processing module to carry
out more instructions, just as an extra kitchen with another set of chefs
would double the number of meals that could be served. This 鈥渟uperscalar鈥�
architecture, which has grown hand-in-hand with RISC technology, allows RISC
chips to begin two or more tasks at once. Several chips, including Hewlett-
Packard鈥檚 Precision Architecture and IBM鈥檚 RS6000, are superscalar.
But these chips need a large amount of extra computing machinery built-in
to manage the extra processing power, and some critics believe that this is
too high a price to pay. Superscalar chips 鈥渉ave never delivered the
performance increases which seemed worth the increase in complexity鈥�, says
Sweetman. The extra management at the chip level requires components that take
up valuable space which could be devoted to more memory or processing modules,
Sweetman says. Reducing the space for memory registers on the chip means that
data must be pumped instead to the computer鈥檚 main memory which, although
bigger, is slower to access.
Last in the list of tricks that chip makers are trying out to increase
processing power is the 鈥渧ery long instruction word鈥�. Going back to the
kitchen analogy, it gives the cooks a composite command that galvanises the
kitchen staff into frenzied activity. Instead of getting a list of
instructions for making an omelette, they might be told something like
鈥淓ggsBreakBeat-SeasonFry鈥� and be expected to get on with it. This differs from
the CISC approach, because the VLIW is generated externally by the compiler,
while CISC instructions are built into the chip itself.
In 1993, Hewlett-Packard and Intel were sufficiently interested in the VLIW
idea to snap up Multiflow, a Connecticut-based company that had gone bust
while developing the technology. 鈥淚t offers potential performance increases
over RISC,鈥� says Ilana Ron of Hewlett-Packard. Beyond that, Intel and Hewlett-
Packard are reluctant even to admit that they are even working on VLIW. Before
Multiflow was bought up, it claimed that it was squeezing 28 instructions per
cycle out of its chips. But Sweetman points out that the company was trying to
develop systems for minicomputers, which contain several processors harnessed
together 鈥� unlike desktop machines, which are built around a single
processor.
There are no guarantees that the VLIW approach will work for desktop
computers. Sweetman suggests that a better approach might be to crank up the
clock speed, or put bigger memories on chips so they can avoid using the main
memory of the computer. Furber is also sceptical. 鈥淚 do not think the world is
going to go VLIW,鈥� he says, 鈥渂ecause a good compiler matched to an efficient
superscalar architecture can go quite a lot further than where we are
苍辞飞.鈥�
Whatever the eventual gains in performance that RISC, pipelining,
superscalar architecture and possibly VLIW may extract from processor chips,
there is a hidden cost. The complexity found in CISC chips has not been lost:
it has merely been passed on to the compiler software. Translating program
code into instructions the chip can understand inevitably causes problems,
which is one reason why PCs and Macs may suddenly crash for no discernible
reason. And as the compiler grows ever more complex, the scope for such errors
rises too.
In an attempt to eliminate these problems, Simon Wiseman and Hugh Field-
Richards at the Defence Research Agency in Malvern have developed the High
Order Language Instruction Set Computer (HOLISTIC). This approach does not
shift complexity between software and the instruction set, they say, but
attempts to remove it altogether. To do this, Wiseman and Field-Richards have
tried to reduce what they call the 鈥渟emantic gap鈥� between high-level
programming languages that human programmers write and the instructions to
which computers respond.
The C programming language, for example, makes use of a concept called a
鈥渟tack鈥� in which programs written in C keep a record of the variables used and
the memory addresses where they are stored. But the stack is an abstraction:
it has no meaning outside the software world. At the hardware level, variables
and addresses are stored not in stacks but in memory registers on the
processor chip and in the main memory. One of the most complex and time-
consuming tasks that a compiler carries out is juggling variables between
registers and the main memory.
The aim of the HOLISTIC approach is to reorganise the chip鈥檚 memory so that
it looks like a stack to the programming language, while the processor sees it
as a series of registers. 鈥淭he trick is to make the two views happen at the
same time,鈥� says Wiseman. 鈥淚f it works then we would not have PCs or Macs
crashing randomly.鈥� Simplifying the compiler is also likely to make life
easier for programmers.
Dedicated chips
Whether the HOLISTIC approach will ever be put to the test in real chips
remains to be seen, however. 鈥淲e got as far as doing the paper design for the
processor and a rough idea of a compiler and then had to stop because funding
dried up,鈥� says Wiseman. In the meantime, he and Field-Richards have applied
for a patent on the technology.
Side-by-side with improvements to general-purpose processors, researchers
are looking at ways to speed up computers using chips designed to do just one
type of task. For example, chips known as digital signal processors handle one
type of input, such as audio or video data from video conferences or games. A
specialised chip can perform its designated tasks much faster than a general-
purpose processor, and by dividing different tasks between chips, designers
hope to put together computers that are much more powerful than machines in
which a single chip does all the work. This trend towards using more
specialised chips could ensure that the limitations of individual chips matter
less.
Perhaps the ultimate multiprocessor machine is the parallel computer, which
breaks down programming tasks into smaller problems and solves them
simultaneously (see 鈥淭ruly, madly, deeply parallel鈥�, 快猫短视频, 24
February). The goal of parallel programming experts is to be able to make a
computer work 10 times as fast by simply building in 10 times as many
processors. If, as some computer scientists believe, this goal is within
sight, it will open up a route around the 0.1 micrometre barrier.
Throw away the clock
THE incessant ticking of a microprocessor鈥檚 internal clock is something
that we might be better off without, according to Steve Furber of the
University of Manchester.
The clock synchronises a microprocessor鈥檚 activities, such as dealing with
software instructions and passing data between modules. But keeping such
strict time causes problems. It means that the chip draws power whether or not
it is doing any useful work, producing large amounts of heat in the process.
In a lap-top computer, much of the precious battery power is wasted turning
the fan that prevents chip overheating.
High demand for power is not the only disadvantage of 鈥渃locked鈥� chips.
Another is that a chip cannot run faster than the slowest command, and chip
designers have to be careful to make sure that every part of an instruction
can be carried out in the same time. If one takes too long it can play havoc
with a series of instructions and cause the chip to lock or the computer to
crash. This is a hazard that grows as the transistors on a chip shrink.
Furber and his team are exploiting changes introduced by RISC designs to do
away with the clock and make each module within the processor autonomous. Each
module now draws power only when it is 鈥渨oken up鈥� by another module to carry
out a task. On chips designed by the Manchester team, the passage of
instructions is not dictated by the clock but negotiated between modules. To
avoid locking the whole system, modules wait a finite time before cancelling a
transfer and trying again or accepting another request.
The value of the technique is that chips consume power only when work is
being done. Existing chips are idle for about 70 per cent of the time, says
Furber. So with the new chips, battery life in laptops and mobile phones could
increase by up to this amount. 鈥淭he whole structure of the computer is wrong
for the things we want it to do now and next,鈥� says Furber.
The Manchester researchers have taken a RISC chip from the British
manufacturer Advanced RISC Machines and prised apart the modules that deal
with instructions for peripherals such as the screen or memory. They made
Amulet 1, the first processor without a clock last year, and its successor,
Amulet 2, was unveiled in November 1995. It is four times as fast as its
predecessor, and as fast as equivalent clocked chips. It is due to make its
first commercial appearance in mobile phones later this year or early
next.